FPGA power management capabilitites

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FPGA power management capabilitites

Postby maryzhu » Fri Jun 02, 2017 7:15 am

Hello all. Thanks for taking up your time to read my post.

When designing ASICs, engineers may use a wide set of architectural and micro-architectural tools and approaches for management of power consumption of the chip:

Retention registers - registers which have a separate power line and store data while the circuit is not powered
Power domain separations - allows for separation of the circuit into distinct power domains which may be powered off independently of each other
Clock domain separation - allows for separation of the circuit into distinct clock domains with clock frequencies tailored for the required performance and power consumption.
Dynamic voltage scaling - allows for reduction of supply voltage when the chip is in "low load" mode.
Dynamic frequency scaling - allows for reduction of clock frequency when the chip is in "low load" mode.
Dynamic clock gating
Few more
I know that there are FPGAs with clock gating capabilities, and I remember that I read once about FPGA which has retention registers, but are these the only ones?

My general question is: what HW power management capabilities for UCC39002DRG4 as the datasheet of http://www.kynix.com/uploadfiles/pdf9675/UCC39002DRG4.pdf are present in the state of the art FPGAs today? I'm not seeking for explanations of the techniques (though good references are welcome), but just want to be updated on the latest FPGA features.

Can anyone help me ? I am very puzzled about this question. I do need your help.

thanks in advance
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